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description the CXA1898Q is an ic developed for analog signal processing in tape recorders. processing for both the recording and playback systems is achieved on one chip. features recording equalizer gp and fp can be adjusted externally. recording mute function agc (automatic gain control) comparator for ams (automatic music sensor) recording/playback equalizer amplifier with 1.7 times speed switching 11-bit serial data interface absolute maximum ratings supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 735 mw operating conditions supply voltage v cc 6.5 to 10.0 v structure bipolar silicon monolithic ic applications all analog signal processing in the cassette decks of tape recorders and compact music centers (applicable to sankyo seiki mfg. co., ltd. yk47r-kf202 r/p head or equivalent) ?1 CXA1898Q e94329b78 recording/playback equalizer amplifier sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic)
?2 CXA1898Q block diagram and pin configuration (top view) iref pb out2 pb fb22 pb fb12 pb inb2 pb ina2 pb ina1 pb inb1 pb fb11 pb fb21 pb out1 ams gain clk latch m2 m1 pl2 pl1 bpb bpa pb mute speed r mute2 r mute1 mute iref pbeq ctl receq ctl receq shift registers gnd agc receq 10k 40k 10k 40k agc gain 19.5db gnd gnd gnd 210k 210k 70k 70k 70k 70k 210k 210k ams ams fil ams out ams gnd fp cal gp cal agc in1 rec in1 agc out1 rec out1 a eq b eq rmute1 i gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd d11 d11 d9 d7 d6 d5 d4 d3 d2 d1 d8 d10 d9 deck a/b d10 speed d9 b eq a eq agc off d8 speed b eq agc gain 19.5db rfc v cc vg gnd agc tc agc in2 rec in2 agc out2 rec out2 d gnd xreset data gnd gnd gnd gnd gnd gnd gnd 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 14 15 16 17 18 19 20 21 22 23 24 13 latches
?3 CXA1898Q pin description pin no. 6 31 symbol dc voltage i/o equivalent circuit description agc in1 agc in2 4.0v i agc signal input. input resistance changes between 47k and 3k i/o resistance 50k v cc 147 3k 47k 4 v cc gnd vgs 6 31 7 30 rec in1 rec in2 4.0v i recording equalizer input. 50k 8 29 agc out1 agc out2 4.0v o agc output pin. agc is applied at ?1dbm or more. 147 9 28 rec out1 rec out2 4.0v o recording equalizer output. 147 7 30 v cc 147 50k v cc gnd vgs 23k 1.8k vgs gnd 8 29 v cc 147 18.8k 500 4 v cc gnd vgs gnd gnd 2 47.8k 5.3k 500 vgs 9 28 v cc 147 40k 500 10 v cc gnd gnd 3 500 2 5p
?4 CXA1898Q 10 a eq ? a deck equalizer switch. low: 120s eq high: 70s eq 10 v cc 147 gnd gnd v cc 11 b eq 2.5v (when open) i b deck equalizer switch. low: normal tape, 120s eq high: cro 2 tape, 70s eq medium: metal tape, 70s eq 53k 12 rmute1 i ? recording mute on/off switch. low: mute off high: mute on * fader function is realized by the external time constant circuit. connects pin 13 (rmute1). 13 14 r mute1 r mute2 15 speed 16 pb mute 5.0v (when reset) (when pin 25 (data) is set to high) o output for recording mute on/off switch control signal. outputs d11 from pin 25 (data). output for recording/ playback equalizer speed switch control signal. outputs d9 from pin 25 (data). low: normal speed high: high speed (1.7 times) output pin for playback mute on/off switch control signal. outputs d7 from pin 25 (data). connects a resistor to v dd for pins 13 to 16. v cc 147 50k v cc gnd gnd 5k 5k 11 2 12 v cc 147 gnd gnd v cc 20k 2 20k 2.7v 50a 14 15 16 4 v dd 5k gnd gnd v cc 4 5k 13 20k pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?5 CXA1898Q 17 bpa 5.0v (when reset) (when pin 25 (data) is set to high) o outputs d6 from pin 25 (data). 18 bpb outputs d5 from pin 25 (data). 19 pl1 outputs d4 from pin 25 (data). 20 pl2 outputs d3 from pin 25 (data). 21 m1 outputs d2 from pin 25 (data). 22 m2 outputs d1 from pin 25 (data). 4 v dd gnd gnd v cc 4 10k 20k 17 18 19 20 21 22 23 latch 26 xreset ? serial data interface latch input. serial data interface reset input. low: reset. at this time serial data outputs (pins 13 to 22) are all open (high). 32 agc tc 0.0v connects a resistor and capacitor for determining agc attack/recovery time constants. 2k gnd v cc 10.5k 25a 23 26 gnd 100a 24k 5p 4 24 25 4k gnd v cc 10.5k 25a gnd 100a 24k 4 32 v cc gnd gnd v cc 2 200 100k 500 500 2 147 2 4 200 5k 24 clk 25 data ? serial data interface clock input. serial data interface serial data input. pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?6 CXA1898Q 34 vg 4.0v signal reference voltage. connects a capacitor for ripple rejection. 60k 34 v cc 147 45k 30k 4 v cc gnd gnd 500 500 2 30k 2 to each vsg 35 v cc 8.0v power supply. 36 rfc 8.0v connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. 38 47 pb out2 pb out1 2.8v o playback equalizer output. 147 35 v cc 36 v cc 147 v cc gnd 3 250 3 to each rfs 38 47 v cc 147 5k v cc gnd gnd 2 3 2 6 500 500 5p pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?7 CXA1898Q 39 46 pb fb22 pb fb21 2.8v connects a capacitor for determining playback equalizer time constants, such as 120s and 70s. 39 46 v cc 147 3 gnd 2k 2k gnd gnd 4 7k 3 4 rfs 40 45 pb inb2 pb ina2 pb ina1 pb inb1 1.4v playback equalizer negative feedback. 105k 41 42 43 44 0.0v i playback equalizer input. 70k 48 ams gain 3.5v connects a resistor for determining ams signal detection level and a capacitor for determining hpf cut-off frequency. 40 41 42 43 44 45 70k 5p v cc 147 gnd v cc gnd 6 v cc gnd 1k 1k 210k 210k 147 v cc rfs 2 10k 10k 6 48 v cc 147 gnd v cc gnd 100k 10 pb fb12 pb fb11 note) the resistance of open collector outputs (pins 2 and 13 to 22) can be also connected to v cc . pin no. symbol dc voltage i/o equivalent circuit description i/o resistance
?8 CXA1898Q electrical characteristics (ta = 25?, v cc = 8.0v, v dd = 5.0v, refer to electrical characteristics measurement circuit) item operating voltage current consumption agc measurement conditions min. typ. max. unit ams playback equalizer amplifier block v cc norm?s, v cc = 8v, no signal pin 32 external r300k / /c47f f = 1khz, vin = ?5dbm pin 32 external r300k / /c47f f = 1khz, vin = ?5dbm pin 32 external r300k / /c47f f = 1khz, vin = 0dbm pin 32 external r300k / /c 47f f = 1khz, vin = ?5dbm pin 48 external r9.1k , c0.015f pin 1 external r100k / /c0.1f f = 5khz, 0db = ?1dbm (at pbeq reference output level) f = 315hz, vin = ?0dbm reference for frequency response f = 2.7khz, vin = ?8.5dbm at 120s?s, 315hz f = 4.5khz, vin = ?3.8dbm at 120s?s, 315hz f = 5.3khz, vin = ?2.5dbm at 120s?s, 315hz f = 9.1khz, vin = ?7.8dbm at 120s?s, 315hz 120s?s, r l = 2.7k f = 1khz, thd + n = 1% 120s?s, r l = 2.7k f = 1khz, vin = ?6.4dbm 120s?s, rg = 2.2k "a" weighting filter 120s?s, rg = 70k agc on output level agc on channel balance agc on distortion agc off output level no signal detection threshold level 120s?s frequency response 120s?s frequency response 70s?s frequency response 120s?s frequency response 70s?s frequency response signal handling total harmonic distortion s/n ratio output offset voltage 6.5 13.5 ?3.0 ?.0 ?.5 ?1.5 ?3.0 ?.1 ?.1 1.8 2.1 ?0.0 55.0 2.4 8.0 18.0 ?1.0 0.0 0.3 ?.5 ?.2 ?1.0 1.3 1.7 3.0 3.6 ?.0 0.3 62.0 2.7 10.0 22.5 ?.0 2.0 1.5 ?.5 ?9.0 2.9 2.9 4.8 5.1 0.7 3.2 v ma dbm db % dbm db dbm db dbm % db v
?9 CXA1898Q db ?6.4 1.5 1.1 7.3 16.4 4.2 9.7 18.2 5.7 8.9 15.8 1.7 12.3 19.5 6.0 16.0 22.5 7.3 14.0 19.7 ?7.9 ?0.0 0.0 ?.2 5.7 13.4 3.0 8.4 15.8 4.5 7.4 13.7 0.2 10.5 16.7 4.9 14.2 20.0 6.1 12.4 17.4 norm?s, 315hz, input level at which reference output can be obtained norm?s, 315hz norm-ns, 315hz, output difference 1ch?ch for ?7.9dbm input f = 3khz at norm?s, 315hz, reference output ?0db f = 8khz at norm?s, 315hz, reference output ?0db f = 12khz at norm?s, 315hz, reference output ?0db f = 3khz at norm?s, 315hz, reference output ?0db f = 8khz at norm?s, 315hz, reference output ?0db f = 12khz at norm?s, 315hz, reference output ?0db f = 3khz at norm?s, 315hz, reference output ?0db f = 8khz at norm?s, 315hz, reference output ?0db f = 12khz at norm?s, 315hz, reference output ?0db f = 5khz at norm?s, 315hz, reference output -20db f = 15khz at norm?s, 315hz, reference output ?0db f = 20khz at norm?s, 315hz, reference output ?0db f = 5khz at norm?s, 315hz, reference output ?0db f = 15khz at norm?s, 315hz, reference output ?0db f = 20khz at norm?s, 315hz, reference output ?0db f = 5khz at norm?s, 315hz, reference output ?0db f = 15khz at norm?s, 315hz, reference output ?0db f = 20khz at norm?s, 315hz, reference output ?0db ?9.4 ?.5 ?.3 3.7 10.4 1.8 6.7 13.2 3.3 5.9 11.3 ?.7 8.3 13.5 3.6 12.0 17.0 4.9 10.5 14.7 reference input level reference output level channel balance norm?s frequency response norm?s frequency response norm?s frequency response cro 2 ?s frequency response cro 2 ?s frequency response cro 2 ?s frequency response metal?s frequency response metal?s frequency response metal?s frequency response norm?s frequency response norm?s frequency response norm?s frequency response cro 2 ?s frequency response cro 2 ?s frequency response cro 2 ?s frequency response metal?s frequency response metal?s frequency response metal?s frequency response recording equalizer amplifier block item measurement conditions min. typ. max. unit dbm
?10 CXA1898Q item recording equalizer amplifier block measurement conditions min. typ. max. unit norm?s, r l 2.7k f = 1khz, thd = 1% norm?s, r l 2.7k f = 1khz, 0db norm?s, rg = 5.1k "a" weighting filter norm?s norm?s, f = 1khz 8db, pin 12 = 3.5v norm?s, f = 1khz 8db, pin 12 = 2.0v a-eq (pin 10) a-eq (pin 10) b-eq (pin 11) b-eq (pin 11) b-eq (pin 11) rmute1-i (pin 12) rmute1-i (pin 12) signal handling total harmonic distortion s/n ratio output offset voltage mute characteristics 1 mute characteristics 2 8.0 57.0 3.6 ?.3 0.0 2.5 0.0 2.2 4.2 0.0 3.5 8.8 0.2 60.6 4.0 ?00 ?.0 0.5 4.4 ?0 ?.3 0.5 v cc 0.5 2.8 v cc 0.5 v cc db % db v control voltage low level 1 control voltage high level 1 control voltage low level 2 control voltage medium level 1 control voltage high level 2 control voltage low level 3 control voltage high level 3 note) norm?s : normal tape?ormal speed norm?s : normal tape?igh speed cro 2 ?s : cro 2 tape?ormal speed cro 2 ?s : cro 2 tape?igh speed metal?s : metal tape?ormal speed metal?s : metal tape?igh speed 120s?s : eq = 120s?ormal speed 120s?s : eq = 120s?igh speed 70s?s : eq = 70s?ormal speed 70s?s : eq = 70s?igh speed db v
?11 CXA1898Q item 11-bit serial data interface block measurement conditions min. typ. max. unit v il (latch/clk/data/xreset) (pins 23, 24, 25, 26) v ih (latch/clk/data/xreset) (pins 23, 24, 25, 26) v ol , i ol = 2ma (max) (pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22) i oz leak current which flows to the output pin when ioz output is open; applied voltage is 10v. (1) f ck (2) t wc (3) t wr (4) t sdk (data ? clk) (5) t hcd (clk ? data) (6) t wd (7) t sld (latch ? data) (8) t hcl (clk ? latch) (9) t hlc (latch ? clk) low level input voltage high level input voltage low level output voltage high level output off- leak current maximum clock frequency minimum clock pulse width minimum reset pulse width minimum data setup time minimum data hold time minimum data pulse width minimum latch setup time minimum latch hold time minimum clock hold time 0.0 3.5 0.0 500 1.5 v dd 0.5 1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 note) v dd is cpu supply voltage 5.0v. the maximum value for v dd is pin 35 (v cc ) voltage. for high level output off leak current, v cc is 10.0v. ? v ? khz
?12 CXA1898Q timing chart for 11-bit serial data interface t wc t wc t wd t hcd t sdk 1.5v 3.5v d1 d2 1.5v 3.5v 1.5v t sld 3.5v 1.5v 3.5v 1.5v t hcl d10 d11 t hlc t wr clk data latch clk data latch xreset
?13 CXA1898Q electrical characteristics measurement circuit ams fil ams out ams gnd fp cal gp cal agc in1 rec in1 agc out1 rec out1 a eq b eq rmute1 i CXA1898Q 14 15 16 17 18 19 20 21 22 23 24 13 2 3 4 5 6 7 8 9 10 11 12 1 rfc v cc vg gnd agc tc agc in2 rec in2 agc out2 rec out2 d gnd xreset data 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 iref pb out2 pb fb22 pb fb12 pb inb2 pb ina2 pb ina1 pb inb1 pb fb11 pb fb21 pb out1 ams gain 10k 0.1 10k 0.1 10k 0.1 2.2 4.7 0.47 0.47 2.7k 10k 5.1k 5.1k 0.1 s7f s12d s20 27k 27k 100k 4.2v 2.0v 2.5v 3.5v 5.0v 0.5v s39 s18b 100 s22a s22b 10k 100 s16 10k s14b 10k s25 s26 s24 s23 s27 s28a rec mute s28b on off metal cro2 norm b eq a eq 120 s 70 s s18a 47k 390k 0.1 0.47 s7d s11 2.2k 377k 0.1 0.47 s7c s10 2.2k 377k 0.1 0.47 s7b s9 2.2k 377k 0.1 0.47 s7a s8 2.2k 377k 100 47 9.1k 2.2 2.7k s12b 0.015 0.018 s14a 100 100 47 0.018 2.2 2.7k s12a 12k 0.1 s12c 10 1k 0.1 10 10 47 300k 5.1k 2.7k 0.47 0.47 4.7 2.2 5.1k s7e 0.1 10k s19 s17a 47k 390k 8.0v s15 10k s13b 10k s13a 100 s17b 100 s21a 100 s21b 10k xreset data clk latch s38 10k 2k 100k 0.1 s37 10k 2k s36 10k 2k s35 10k 2k s34 10k 2k s33 10k 2k s32 10k 2k s31 10k 2k s30 10k 2k s29 10k 2k dc output gnd gnd s501 s502 s503 s504 s505 ac output 100k buf 30db amp "a" w eighting filter audio (22.2hz-22.2khz) filter 1khz band pass filter (20db) tl072 gnd 600 att ?db s1b s1a att ?db s3b s3a att ?7db s6b s6a att ?9db s4b s4a att ?0db s2b s2a ac input clk latch m2 m1 pl2 pl1 bpb bpa pb mute speed r mute2 r mute1
?14 CXA1898Q application circuit iref pb out2 pb fb22 pb fb12 pb inb2 pb ina2 pb ina1 pb inb1 pb fb11 pb fb21 pb out1 ams gain clk latch m2 m1 pl2 pl1 bpb bpa pb mute speed r mute2 r mute1 mute iref pbeq ctl receq ctl receq latches 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k gnd 47k shift registers gnd agc receq 10k 40k 10k 40k agc gain 19.5db gnd gnd gnd 210k 210k 70k 70k 70k 70k 210k 210k ams ams fil ams out ams gnd fp cal gp cal agc in1 rec in1 agc out1 rec out1 a eq b eq rmute1 i gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd d11 d11 d9 d7 d6 d5 d4 d3 d2 d1 d8 d10 d9 deck a/b d10 speed d9 b eq a eq agc off d8 speed b eq agc gain 19.5db rfc v cc vg gnd agc tc agc in2 rec in2 agc out2 rec out2 d gnd xreset data deck-a pb-head bias osc rec pb gnd rec pb gnd 10k 12mh 820p 180p 150p gnd 10k 12mh 820p 180p 150p gnd r/p-head deck-b 12k 10k 2.2 0.018 47 100 gnd gnd gnd 47 100 gnd 0.018 10k 2.2 gnd 1k 0.1 0.1 100k 100k 27k 27k 0.47 0.1 4.7 10k 2.2 0.1 10k gnd gnd gnd gnd v dd or v cc 1k 2.7k 0.47 0.1 4.7 10k 2.2 100 gnd 100k gnd gnd v dd 2.2 2.2meg 47 gnd gnd gnd v cc gnd gnd gnd gnd gnd gnd gnd gnd 40 39 38 37 41 42 43 44 45 46 47 48 14 15 16 17 18 19 20 21 22 23 24 13 2 3 4 5 6 7 8 9 10 11 12 1 25 26 27 28 29 30 36 35 34 31 32 33 gnd gnd 2.7k 10 47 v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc v dd or v cc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?15 CXA1898Q 1. system control mode playback and recording equalizer (1) playback equalizer (120s/70s) deck-ab (serial data d10 (pin 25)) a-eq (pin 10) b-eq (pin 11) l h l m/h l h 120s (a deck) 70s (a deck) according to a eq control 120s (b deck) 70s (b deck) according to b eq control (2) recording equalizer (normal, cro 2 , metal) b-eq (pin 11) rec mode l normal (type i) m cro 2 (type ii) h metal (type iv) (3) recording mute (pin 12) rec mute control voltage mute off gnd vcl 0.5v ?db attenuation 2.0v mute on 3.5v vch v cc muting is achieved by varying the recording equalizer amplifier gain just like an electronic volume, according to the dc voltage applied to the rec mute pin. (4) fp cal (pin 4) the standard resistor setting is 27k , but when resistance value is larger, fo (hz) is low, and when resistance value is smaller, fo (hz) is high. (5) gp cal (pin 5) the standard resistor setting is 27k , but when resistance value is larger, gain is larger, and when resistance value is smaller, gain is smaller.
?16 CXA1898Q 2. 11-bit serial data interface the data signal is taken in at the rising edge of the clk signal. the data signal is taken in to the internal shift register when the latch signal is low. (outputs (pins 13 to 22) hold the previous value while the latch signal is low.) the internal shift register data is latched and output in parallel at the rising edge of the latch signal. (internal shift register data is loaded while the latch signal is high.) the clk signal of 11th bit should fall after the latch signal rises. reset is done when the xreset pin is low. (asynchronous method) outputs (pins 13 to 22) are all high (open) during reset. d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 m2 m1 pl2 pl1 bpb bpa pb-mute agc-off speed deck-ab rec-mute pin 22 pin 21 pin 20 pin 19 pin 18 pin 17 pin 16 pin 15 pin 14/pin 13 l l l l l l l agc function stops low, normal speed a deck selected low mute off h (open) h (open) h (open) h (open) h (open) h (open) h (open) agc function operates high (open) 1.7 b deck selected high (open) mute on output pin input set at low input set at high output data (pin 25) control signal d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 clk (pin 24) data (pin 25) latch (pin 23) xreset (pin 26) d11
?17 CXA1898Q make sure that rfc is 5.5v or more and xreset is 1.5v or less, and 1s or more when resetting by applying cr time constant to xreset (pin 26) and turning power on. when resetting with cpu or other when power is turned on examples of agc control during timer recording (1) resets when power is turned on (agc function operates). (2) agc is turned off after agc inputs (pins 6 and 31) rise. (external capacitor charge of agc tc is discharged.) (3) agc is turned on and timer recording begins. 1 s or more 1.5v or less 5.5v or more rfc (pin 36) xreset (pin 26) 1 s or more 5.0v 5.5v or more rfc (pin 36) xreset (pin 26) 0v
?18 CXA1898Q circuit diagram for 11-bit serial data transfer evaluation tool d11 h l d10 h l d9 h l d8 h l d12 h l d13 h l d14 h l d15 h l 6 8 9 10 11 12 13 14 2 3 4 5 6 7 1 xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (1) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (2) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (3) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 xq2 q2 xpr2 clk2 d2 xr2 v dd v ss xq1 q1 xpr1 clk1 d1 xr1 74hc74 (4) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 y3 a3 b3 y4 a4 b4 v dd v ss y2 b2 a2 y1 b1 a1 74hc00 8 9 10 11 12 13 14 2 3 4 5 6 7 1 y3 a3 b3 y4 a4 b4 v dd v ss y2 b2 a2 y1 b1 a1 74hc08 (2) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 y3 a3 b3 y4 a4 b4 v dd v ss y2 b2 a2 y1 b1 a1 74hc08 (1) 8 9 10 11 12 13 14 2 3 4 5 6 7 1 y4 a4 y5 a5 y6 a6 v dd v ss y3 a3 y2 a2 y1 a1 74hc04 r5 10k on off start 3 on off reset c5 0.1 4 c12 0.1 c9 0.1 c8 0.1 r3 10k r6 10k c4 0.1 15 c14 0.1 c13 0.1 c20 0.1 5 13 100 r16 12 1 14 8 9 10 11 12 13 14 2 3 4 5 6 7 1 q1 clock reset q9 q8 q10 q11 v dd v ss q2 q3 q4 q7 q5 q6 q12 74hc4040 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 xa2 b2 xres2 xq2 q1 c1 r/c1 v dd v ss r/c2 c2 q2 xq1 xres1 b1 xa1 74hc123 15 16 8 9 10 11 12 13 14 2 3 4 5 6 7 1 b0 a0 b1 a1 a2 b2 a3 v dd v ss about a>bin a=bin a ?19 CXA1898Q timing chart for 11-bit serial data transfer evaluation tool dummy d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 2s count reset clock stop (14) reset/clock stop and count reset (15) data hc165 (16) clock (17) = (8) (18) (19) latch (13) (12) (11) hc123 (10) a = b, h (9) (8) clk gate cont. (7) s/l (6) = (4) (5) (4) (3) start pulse (2) clk (1) clk
?20 CXA1898Q 3. ams (1) ams output logic ams out (pin 2) is an open collector output pin. when a 2.2k resistor is connected to v dd : low : approximately 0.5v (i ol = 2ma (max.)) high : v dd fig. 1 shows the ams block diagram. fig. 1 ams block diagram fig. 2 shows the frequency response of the signal output from hpf. fig. 2 frequency response detection status ams out (pin 2) signal detection l no signal detection h 2 3 1 48 pb out1 pb out2 20k 20k sa lpf det 25khz 100k gnd v dd v dd v dd gnd ams gnd ams out ams fil c1 r1 r2 c2 r3 hpf ams gain inside ic f c g 10 1khz 25khz 100khz gain (db) f (hz)
?21 CXA1898Q (2) ams level setting the ams level is set by adjusting hpf gain and cut-off frequency with the external resistor and capacitor at pin 48. g and fc in fig. 2 are obtained from the following formula. g = 20log (1 + 100k/r) [db] ?(1) fc = 1/ (2 ? ?c ?r) [hz] full-wave rectifier is applied for the signal at det. signal detection time is set by the time constant of pin 1 external resistor and capacitor. det signal detection level: = ?.5dbm (typ.) = playback equalizer reference output level + ams level + hpf gain ?(2) playback equalizer reference output level of ?1dbm is 0db. ex.) to set ams level at ?5db, determine and set the constant for pin 48 external resistor. (calculate assuming pbout1 = pbout2) first, get the required hpf gain from formula (2). ?.5dbm = ?1dbm + (?5db) + hpf gain, so hpf gain = 38.5db. next, get pin 48 external resistance from formula (1). 38.5db = 20log (1 + 100k/r), so r 1.2k , and external resistance is 1.2k .
?22 CXA1898Q quiescent current consumption vs. supply voltage v cc -supply voltage (v) 25 24 23 22 21 20 19 18 17 16 15 i cc -quiescent current consumption (ma) 6 7 8 9 10 11 example of representative characteristics pb in pb fb1 pb fb2 pb out playback equalizer frequency response frequency (hz) 65 60 55 50 45 40 35 30 25 gain (db) 20 50 100 200 500 1k 2k 5k 10k 20k 50k 120s ?ns 120s ?hs 70s ?ns 70s ?hs m v cc = 8v 0.018 2.2k 0.47 47 100 2.2
?23 CXA1898Q recording equalizer frequency response frequency (hz) 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 ? output response (db) 20 50 100 200 500 1k 2k 5k 10k 20k 50k v cc = 8v 0db = norm ?ns, 315hz, ?0dbm (tape) (speed) norm cro2 metal ns ns ns 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 ? 20 50 100 200 500 1k 2k 5k 10k 20k 50k v cc = 8v 0db = norm ?ns, 315hz, ?0dbm (tape) (speed) norm cro2 metal hs hs hs recording equalizer frequency response frequency (hz) output response (db)
?24 CXA1898Q rmute1 (pin 1) voltage 0.0 1.0 2.0 3.0 4.0 5.0 6.0 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 output level vs. mute voltage v cc = 8v (tape) (speed) norm? ns 0db = reference output level +8db f = 1khz output level (db) ams no signal detection level frequency response frequency (hz) 30 25 20 15 10 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 ams input level (playback equalizer output level) (db) 20 50 100 200 500 1k 2k 5k 10k 20k 50k v cc = 8v 120s ?ns ams out 5v 0db = ?1dbm, 315hz (playback equalizer reference output level) a b a : pin 48 for r9.1k, c0.015 b : pin 48 for r1k, c0.1 ams gain ams fil ams out 0.1 100k 100k to5v 2 48 1 a : 0.015 9.1k b : 0.1 1k
?25 CXA1898Q agc output response 10 5 0 ? ?0 ?5 output level (dbm) ?5 ?0 ?5 ?0 ?5 ?0 ? input level (dbm) agc off agc on v cc = 8v 1khz 32 47 300k agc tc recording equalizer total harmonic distortion ?5 ?0 ? 0 5 10 output level (db) t.h.d. + noise (%) 2.0 1.0 0.5 0.2 0.1 v cc = 8v norm ?ns mode r l = 2.7k w 1khz 0db = ?0dbm playback equalizer total harmonic distortion ?0 ?5 ?0 ?5 ?0 ? output level (db) t.h.d. + noise (%) 2.0 1.0 0.5 0.2 0.1 v cc = 8v 120s ?ns mode r l = 2.7k w 1khz
?26 CXA1898Q package outline unit: mm sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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